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The design and measurement of a high-speed optical receiver is presented. The intrisically low speed of a silicon photodiode is increased by a new photodiode structure which combines a high speed and a high responsivity. On top of this, an equalizer is used to increase the attainable bit rate even more. The receiver, existing from a photodiode, TIA, equalizer and post amplifier is integrated in a...
This paper presents a switched-capacitor DeltaSigma analog-to-digital converter, achieving a dynamic range of 84 dB and a bandwidth of 1 MHz for a power consumption of 17 mW. A cascade 3-1 topology allows aggressive noise-shaping without imposing too stringent specifications on the amplifiers. The design is implemented in a 1 V, 65 nm standard CMOS technology. The use of a novel symmetrical bootstrapped...
An optical receiver with monolithically integrated photodiode in a standard 0.18 mum CMOS technology is presented. At 1.2 Gbit/s, the optical sensitivity is -8 dBm for a BER of 10-12, while the off-chip output amplitude is 500 mVpp into a 50 Omega load. The post-amplifier can handle bitrates up to 5 Gbit/s with a BER of 10 -12 and a dynamic range larger than 41 dB. Current consumption of the complete...
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