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A 2.5-Gb/s clock and data recovery (CDR) circuit is presented, which employs an oversampling technique to recovery the data and an offset-frequency calibrated technique to compensate the frequency error between input rate and output clock. The offset-frequency calibrated technique is based on the ΔΣ modulated phase-lock-loop topology that can calibration frequency offset ±200 MHz. Simulated by 0.18-μm...