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Today, a great concern for the integration of high-frequency systems are the problems associated with the synchronization difficulties. The VCO block of PLLs is the primary source of timing jitter and this work addresses issues significant to the design of VCOs with Single-Ended Control in PLLs. The main goal of this work is to develop Two high frequency CMOS PLLs in 0.13μm technology. The advantage...
In this paper, a blind video watermarking algorithm based on 3D wavelet transform and Human Visual System (HVS) model is proposed. The proposed method is based on extracting temporal characteristics of video signal and using it to adjust spatial features of each frame. These frames are designed based on HVS model embed the message. Then the message will be extracted from video watermarked through...
In this paper, a general delay locked loop based frequency multiplier is presented. No LC-tank and ring oscillator are used in the proposed design such that the power dissipation and chip area are drastically reduced. Moreover this multiplier does not require external component and it is primarily intended for ASIC design. All the simulation results are based upon UMC 0.13μm CMOS process at 1.2 V...
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, Trivium stream cipher is implemented using the Sense Amplifier Based Logic (SABL) styles. Trivium was submitted to eSTREAM project in 2005 and then selected as one of four finalists of competition on April 15, 2008. The cipher is designed by two submicron technologies and simulated by HSpice...
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