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This paper investigates the optimum Booth integer multiplier for low power applications. Booth radix-4, radix-8 and radix-16 were compared for area, speed and power using standard-cell ASIC design flow and 28nm CMOS technology. All of the investigated designs were implemented in RTL, fully verified and then synthesized using 28nm standard-cell libraries which have low leakage slow cells, regular leakage...
A universal floating-point fused dot-product (UFDP) unit is presented that is capable of performing floating-point multiplication and addition or subtraction operations on two pairs of data, floating-point multiply add operation on three data items, floating-point multiplication of two data items and floating-point addition or subtraction of two data items. The proposed UFDP unit could be used as...
This paper presents a high-throughput, contention-free, low-power, Radix-2 decimation in frequency fast Fourier transform core implemented in 28nm industry representative standard-cell process. It utilizes an algorithm to eliminate memory access contention and maximize throughput by eliminating bubbles in the butterfly's pipeline. The implementation of the FFT core is presented, including timing and...
This paper describes two fused floating-point operations and applies them to the implementation of fast Fourier transform (FFT) processors. The fused operations are a two-term dot product and an add-subtract unit. The FFT processors use "butterfly” operations that consist of multiplications, additions, and subtractions of complex valued data. Both radix-2 and radix-4 butterflies are implemented...
This paper extends the consideration of fused floating-point arithmetic to complex multiplication, an operation that is frequently used in DSP. There are two basic approaches to complex multiplication: (1) the conventional method that uses 4 real multiplies and 2 real adds and (2) Golub's method that uses 3 real multiplies and 5 real additions. This paper compares discrete implementations using individual...
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