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This paper describes a unified popcount/bitscanforward/bitscanreverse datapath circuit designed for 2.1GHz operation with total power consumption of 6.5 mW, targeted for 65 nm 64-bit microprocessor execution cores. The unified datapath uses a hybrid 3:2 compressor-based Wallace tree to count the number of '1's in the 64-bit input, along with a novel encoding scheme that enables reuse of the same tree...
In a 4th-generation 65nm Intel Pentiumreg4 processor, the previously low voltage swing, 2times microprocessor frequency, AGU and ALUs are replaced with domino-logic-based architectures optimized for low latency, 2times frequency, and lower power. These redesigned AGU/ALUs reduce normalized dynamic power by 50% over the previous generation, and together with the similarly optimized integer register...
In this paper, we motivate the concept of comparing very large scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a need to make appropriate selection at the beginning of the design process. The estimation is quick, not requiring extensive simulation or use of computer-aided design tools, yet sufficiently accurate to...
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