The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Wide-VDD-range processors offer high energy efficiency for varying embedded workloads. But reducing the VDD of the cache as aggressively as the VDD of the CPU logic is not straightforward, since standard 6T SRAMs cease to operate at lower VDDs. We implement a data and instruction filter cache, using logic cells located in the CPU VDD domain, to permit the level-1 (L1) cache to be reliably powered...
Massive Multiple-Input Multiple-Output (MIMO) systems have been shown to improve both spectral and energy efficiency one or more orders of magnitude by efficiently exploiting the spatial domain. Low-cost RF chains can be employed to reduce the Base Station (BS) cost, however this may require additional baseband processing to handle induced distortions due to the hardware impairments. In this article...
A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage,...
Future mobile terminals are expected to support an ever increasing number of Radio Access Technologies (RAT) concurrently. This imposes a challenge to terminal designers already today. Software Defined Radio (SDR) solutions are a compelling alternative to address this issue in the digital baseband, given its high flexibility and low Non-Recurring Engineering (NRE) cost. However, the challenge still...
This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured...
This paper describes a hardware efficient linear precoder for Massive MIMO Base Stations (BSs) comprising a very large number of antennas, say, in the order of 100s, serving multiple users simultaneously. To avoid hardware demanding direct matrix inversions required for the Zero-Forcing (ZF) precoder, we use low complexity Neumann series based approximations. Furthermore, we propose a method to speed-up...
An Orthogonal Frequency-Division Multiplexing (OFDM) based multi-user massive Multiple-Input Multiple-Output (MIMO) system is considered. The problem of high Peak-to-Average Ratio (PAR) in OFDM based systems is well known and the large number of antennas (RF-chains) at the Base Station (BS) in massive MIMO systems aggravates this further, since large numbers of these Power Amplifiers (PAs) are used...
In July 2000 the five-year Swedish national “Socware Research & Education Program” was started. One of the aims of the program was to develop an innovative unique educational curriculum in System-on-Chip design. The program was targeted at undergraduate and graduate. In total the program received USD $15 million funding. In 2005 the program entered a new phase; more than 500 Master's students...
A transceiver suitable for devices in wireless body area networks is presented. Stringent requirements are imposed by the high link loss between opposite sides of the body, about 85 dB in the 2.45 GHz ISM band. Despite this, minimum physical size and power consumption are required, and we target a transceiver with 1 mm2 chip area, 1 mW active power consumption, and data rate 250 kbit/s. The receiver...
This article presents an architecture of a Digital Front-End Receiver (DFE-Rx) for the next-generation mobile terminals. A main focus is placed in flexibility, scalability and concurrency. The architecture is capable of detecting, synchronizing and reporting carrier-frequency offset, of multiple concurrent radio standards. The proposed receiver is fabricated in a 65 nm CMOS low power high-VT cell...
In very-large multiple-input multiple-output (MIMO) systems, the base station (BS) is equipped with very large number of antennas as compared to previously considered systems. There are various advantages of increasing the number of antennas, and some schemes require handling large matrices for joint processing (pre-coding) at the BS. The dirty paper coding (DPC) is an optimal pre-coding scheme and...
This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations....
Various synthesis strategies relying on conventional standard-cell libraries (SCLs) are evaluated in order to minimize the energy dissipation per operation in sub-threshold (sub-VT) systems. First, two sub-VT analysis methods are reviewed, both of which allow to evaluate the energy dissipation and performance in the sub-VT regime for designs which have been synthesized using a 65-nm CMOS SCL, characterized...
This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.