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Networks-on-chips (NoC) have been introduced as a remedy for the growing problems of current interconnection VLSI chips. Being a relatively new domain in research, simulation tools for NoC are scarce. To fill the gap, we use network simulator NS-2 for simulating multi protocol label switching in NoC, especially at high level chip design. The huge library of network elements with its flexibility to...
In this paper, we discuss the difficulties Reserved Bandwidth Mechanisms for networks-on-chip by MPLS packet-forwarding technologies. Then, we compare these mechanisms in Network-On-Chip that is based on applying the well-known MPLS technology of large-scale computer networks to the on-chip environment. The NS-2 network simulator is used to evaluate the concept for a typical communications scenario...
We propose a combination of Fat-Tree topology and Bisection routing in MPLS network-on-chip which can increase Communication load and quality of service which is suitable for multimedia applications. We compare the performance of IP and MPLS Fat-Tree-based Network-on-chips. The simulations of the architectures are done with two-dimensional Fat-Tree topologies that used MPLS base recovery mechanism...
In ten years ago accomplished many efforts to improve the power of intrusion detection systems (IDS). These systems divided in three important components named as Information Collection, Detect and Response. We propose in this paper creating an extra component named Postprocessor in IDSs for improve the flexibility of them. Also a protocol is proposed in physical layer in TCP/IP model to send the...
As CMOS technology scales down into the deep submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. In this paper we compare four reconfigurable fault recovery mechanism and path restoration schemes, namely, Haskin, Makam, Simple Dynamic and Shortest Dynamic...
We propose a combination of Mesh topology and Bisection routing in MPLS and IP network-on-chip which can increase Communication load with quality of service which is suitable for multimedia applications. We compare the performance of 2d-Mesh architectures in the sense of on chip network design methodology. The simulations of the architectures are done with two-dimensional Mesh topologies that used...
As CMOS technology scales down into the deep submicron (DSM) domain, devices and interconnects are subject to new types of malfunctions and failures that are harder to predict and avoid with the current system-on-chip (SoC) design methodologies. We propose a combination of a topology and Multi-path routing which can increase fault-Tolerant and Communication load which is suitable for multimedia applications...
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