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This paper presents a design of a transmitter pulse generator UWB-Ultra Wide Band in standard 180 nm MOSIS/CMOS technology. We proposed a pulse generator using Phase-Frequency Detector (PFD) that is designed using a modified architecture TSPC (True Single-phase Clock) positive edge triggered D Latch. The operation range and power consumption PFD is 45 ??W to 2 mW, from 200 MHz to 5 GHz, respectively,...
This paper describes the design and simulation, using the SONNET tool, of a new inductor structure with crossed segments (cross). In order to compare, the new and conventional rectangular inductors were designed using a 0.35 mum CMOS technology. To make a fair comparison we fixed the segment width and spacing to 10 mum. After the design, the cross inductor presents an area of 120times140 mum2, an...
A study of delay deviation in CMOS tapered buffers due to transistor mismatching is presented. Theoretical relations for the delay deviation were derived from the buffer and transistor parameters. To validate those relations, and to investigate the buffer behavior, special test structures consisting of tapered buffers configured as ring oscillators were designed in a 0.35 mum CMOS technology. The...
New structures to be applied with the extended true-single-phase-clock (E-TSPC) CMOS circuit technique, an extension of the traditional true-single-phase-clock (TSPC) are presented. These structures, formed by the connection of proper data paths, allow circuits to handle data with rates that are twice the clock rate. Examples of circuits employing such structures are shortly reported and to illustrate...
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