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In order to implement more advanced nonvolatile memory device, many studies have been devoted to improve program/erase speed, endurance, and retention characteristics of nitride-based SONOS flash memory. As the CMOS device size shrinks down, the oxide-nitride-oxide (ONO) multi-layer where charge storage takes place in discrete traps in the silicon nitride layer needs the optimization of thickness...
A new 2-bit/cell SONOS flash memory device is designed and simulated with a numerical simulation tool. The device has a recessed channel and a supplementary gate named a select gate. The select gate is appended to enhance the program efficiency by source-side injection (SSI) as well as to separate the charge storage nodes physically. The designed structure looks like a folded form of conventional...
A SONOS flash memory having locally-separated vertical channels is investigated. The vertical SONOS flash memory has a scaling issue related with the fin width. As the fin width is shorter, electrical interference between paired cells (PCI) is severer. To overcome PCI, we propose the locally-separated vertical channel SONOS (LSVC SONOS) structure. We demonstrate reliable operation of LSVC SONOS using...
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