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An 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing...
A 12b two-step pipelined SAR ADC reports a 66.7dB SNDR and an 86.9dB SFDR for a 5MHz sinusoidal input at 160MS/s. A digital background calibration based on opportunistic PN injection treats both DAC mismatch and residue-amplifier gain errors. The calibration enables a significant downsizing of the ADC input capacitance to yield a wideband, highly linear input network and an over-80dB SFDR while digitizing...
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