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Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active...
We report our latest activities of low-temperature III/V-to-Si direct wafer bonding assisted by chemical-mechanical polishing (CMP) and O2 plasma activation. We show here the optimized process flow for fusion bonding of InP epitaxial wafers and dies onto silicon (Si) substrate covered with oxide layer of varying thickness. High yield and low cost die-to-wafer bonding is achievable in the near future.
High-k/Ge interfaces are significantly improved through a new interface engineering scheme of using both effective pre-gate surface GeO2 passivation and post gate dielectric (post-gate) treatment incorporating fluorine (F) into high-k/Ge gate stack. Minimum density of interface states (Dit) of 2 times 1011 cm-2eV-1 is obtained for Ge MOS capacitors. Hole mobility up to 396 cm2/Vs is achieved for Ge...
A thin palladium layer (~20 A) was selectively formed on top of amorphous germanium film before annealing and the effects of palladium layer on the lateral crystallization behavior of the amorphous germanium film were investigated through optical microscope, Raman spectroscopy, transmission electron microscopy, energy dispersion X-ray spectroscopy and selective area electron diffraction. Lateral crystallization...
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