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A methodology to predict the process e-test parameters corresponding to each die (even in regions of the die where e-test structures are not available) from die test measurements for analog/RF systems is developed. The methodology provides diagnosis of process variations with higher spatial resolution in volume manufacturing over other techniques due to the availability of manufacturing test data...
Quality improvement and cost reduction in the overall IC manufacturing and test processes are being continuously sought. Outlier screening methods can address both of these needs. As technology scales, it has become increasingly difficult to screen outliers without excessive Type I or II errors. Hundreds of parameters are collected at wafer probe, but there lacks a systematic way of selecting outlier...
Today's SoC designs contain many types of circuitry, each with various test types. This article revisits the classic test escape models and highlights their limitations in a test environment with different types of circuits and different test types with overlapping coverage. A new methodology for test escape rate prediction is presented.
The Williams and Brown model has long been the gold standard for estimating test escape rate as a function of yield and fault coverage. However, today's test programs have a number of differing test types, often with overlapping failing unit detections. This paper details the development of a method which permits test escape rate predictions based on product yield and multiple overlapping test coverages.
A method to model and de-rate product DPPM using existing production EFR (early failure rate) and burn-in data is proposed. This approach incorporates multiple classes of reliability fail modes. Changes in process, test, or design may then be employed to optimize product outgoing defect levels. These changes will be based on the defect acceleration kinetic parameters, instead of just the reliability...
Burn-in and the concomitant post-burn-in retest are significant cost adders to the overall IC manufacturing and test process. Methods to reduce burn-in capacity are continually sought. Traditional outlier screens such as fixed-limit analyses with parametric or non-parametric statistics, when applied to the newest technologies, result in excessive Type I or II errors which cannot be tolerated. In this...
The ability to meet ever more demanding customer quality and reliability requirements is becoming increasingly difficult with each advancing technology generation. This issue becomes more complex as customer applications and requirements become more varied for the same basic technology. The customer applications range from cell phones and PDAs to servers to automotive. The reliability requirement...
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