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The primary somatosensory cortex (S1) projects to the thalamus and brainstem somatosensory nuclei and modulates somatosensory information ascending to the S1 itself. However, the projections from the S1 to the brainstem second-order somatosensory neuron pools have not been fully studied. To address this in rats, we first revealed the somatotopic representation of orofacial areas in the S1 by recording...
In this paper, we have proposed, fabricated and characterized a parallel electron beam micro-column with single-stranded carbon nanotube (CNT) filed emitters. The integrated micro-column consists of a self-aligned CNT field emitter array (FEA), and a multi-layered electrostatic Si focusing lens array. In our design, the emitters, gate and electrostatic lens array are electrically isolated, and each...
Micromachining is an extended IC fabrication based on photo-fabrication, deep etching, anodic bonding and other advanced process technologies. This is used to produce MEMS (Micro Electro Mechanical Systems) featuring multi-functions, small size and low cost. Nanostructures such as CNT (Carbon Nano Tube) can be also included in the MEMS by nanomachining. MEMS are used as value added key components...
In this paper, we present a photothermal transducer consisted of an ultrathin Au/Si bimetal cantilever as a resonator with a total thickness of 45 nm and quality factor of -12000. Due to the high quality factor and small size, this transducer is sensitive to photothermal effect and its thermal response frequency can be up to 140 kHz. It is demonstrated that the irradiation of weak laser can enhance...
This paper reports on the development and evaluation of various multi-probes consisted of silicon cantilevers with different types of tips made of platinum, ruthenium, chromium and diamond for probe-based ultra-high-density ferroelectric data storages beyond 1 Tbit/inch . The metal probes can write and read the data bits on a medium with contact operation. We performed wear tests on the various tips...
The process integration schemes for CMOS FinFET fabricated on bulk Si substrate are discussed from the viewpoints of device size scalability and short channel effect control. The trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime. A novel punch through stopper (PTS) formation process was introduced to the bottom of the channel region to scale the gate...
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