The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A between-pair skew compensator for parallel data communications is presented. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a voltage controlled wide-bandwidth data delay line. A 5Gb/s sub-bit between-pair skew compensator in 0.13μm CMOS occupies 0.03mm2 active die area and dissipates 22.5mW.
This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced...
The paper presents analysis of the input impedance, as well as the input capacitance and output resistance of diode doublers and multistage rectifiers. Tradeoffs between device sizes and the number of rectification stages are presented with an emphasis on low cost impedance matching. As a result, it is possible to achieve higher efficiency in RF to DC conversion with low cost impedance matching by...
This paper presents a continuous-time adaptive FIR filter as a fractionally spaced receiver equalizer. Inverter-based delay units with active-inductor load (INV-AIL) are proposed to implement the tap delay line for the bandwidth enhancement. A pulse extraction technique is employed for the equalizer adaptation to different channel characteristics. Implemented in a standard CMOS 0.25-mum process, the...
A repeater has been developed for 125Mbaud twisted pair data communication with binary signal levels. The repeater includes an adaptive equalizer and a driver. This architecture operates from a 2V supply while consuming less than 6mA of current in the equalizer section and 12mA in the driver section. The active die area is less than 0.04mm2in a 0.21 µ digital CMOS process. For 100m UTP5 cable the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.