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This paper presents measured, simulated and calculated third-order intercept point (IP3) on a 90-nm RF CMOS technology. The IP3 sweet spot is actually at a VGS lower than zero K 3gm point. This VGS difference is attributed to the nonlinear output conductance and the cross terms using a Volterra-series-based IP3 expression. The impact of these nonlinearities is quantified using simulated I-V and...
This work examines the intermodulation linearity of 90 nm RF CMOS using IP3 measurement, BSIM4 based simulation, and first order theory. VGS, VDS, and device width dependences are examined. Guidelines to accurately identifying the sweet spot biasing current for larger devices used in RFIC design are provided.
This work examines the differences between the gd0 and gm referenced drain current excess noise factors in CMOS transistors as a function of channel length and bias. Using standard linear noisy two-port theory, we present a simple derivation of noise parameters. The results are compared with the well known Fukui's empirical FET noise equations. Experimental data on a 0.18 mum CMOS process are measured...
This paper presents an improved algorithm to solve the general 4-port parasitics de-embedding problem. Experimental results on 0.13 mum RF CMOS device are presented. For the device examined, gate resistance extracted from open-short results is 40% lower than that extracted from 4-port results. The reciprocity and symmetry of the 4-port parasitics are also examined
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