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We investigated threshold voltage shifts after program pulse in charge trap flash memory by measuring drain current changes. We have found threshold voltage shifts can be characterized as a function of not only the materials of tunnel oxide, trap layer, blocking layer, but also physical parameters like device size and electrical measurement environment such as program voltage target and gate bias...
A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si3N4/Al2O3/Si3N4 (NAN) was adopted as a trap layer in place of single Si3N4 layer in TANOS structure [1]. Compared to the reference structure of single Si3N4 trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (10V),...
For the first time, we have demonstrated the feasibility of charge trap-based devices with ultra-thin tunnel oxide for high density DRAM application. Experimental results using direct tunneling scheme show good memory characteristics such as long retention time (>1000sec), large memory window (>1V), non-destructive read, high endurance, and acceptable programming speed (~100ns). Further improvement...
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