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A low power linearity-ratio-independent DAC for ΔΣ data converters is proposed in this paper. By using a gain-boosted sub-threshold inverter as an amplifier, circuit power consumption is decreased significantly. The sensitivity of the differential DAC output linearity on circuit mismatches is reduced by using mutually-referred inputs. In a 0.13um CMOS technology, Monte-Carlo analysis and transistor-level...
We investigate modulation-based parallel delta-sigma (ΔΣ) converters for wideband A/D conversion applications. A code division parallel ΔΣ conversion method is proposed, where each path consisting of a ΔΣ modulator operates on an input signal modulated with different binary code. In contrast to standard Hadamard based modulation schemes, the design provides flexibility in choosing the number of parallel...
We propose a low-power active switched-capacitor (SC) implementation of the loop filter for PLL applications. Control voltage ripples caused by current mismatches are eliminated. Sub-threshold inverters are employed as the active components of the filter resulting in very low circuit power consumption. Moreover, 1/f noise of the inverter amplifier is suppressed by the SC auto-zeroing. Transistor level...
We consider optimal resource allocation for wireless video sensors (WVSs), including the image sensor subsystem into the system analysis. By assigning a power-rate-distortion (P- R-D) characteristic for the image sensor, we build a comprehensive P-R-D framework for WVS optimization. Within the scope of the developed framework, we solve the problem of how to allocate power among the image sensor, compression,...
An image sensor design with pixel-level sigma-delta (SigmaDelta) conversion employing four transistors at each pixel where the feedback charge transfer is realized through the parasitic capacitances of an inactive transistor is presented. This architecture is a relatively simple and robust design where the only analog components required outside of the pixel array are shared row comparators and a...
We propose a CMOS image sensor pixel readout method that eliminates the need for external correlated double sampling circuit that is used in existing CMOS active pixel sensor (APS) design. The pixel transistor count in the proposed design is equal to the standard APS thus retaining high fill factor. The design employs reconfigurable differential-input readout amplifier that may be used in both the...
A methodology is proposed to reduce power/ground and substrate coupling noise by randomizing the clock signal. A pseudo-random number generation algorithm is used to produce a pseudo-random clock. A probability adjustment technique is introduced to compensate for the speed loss, permitting the average frequency of the pseudo-random clock to be determined. The proposed method achieves more than 24...
Driven by the defense, medical, and automotive markets, the demand for low-cost, low-overhead sensors for precision signal acquisition has increased by more than 200% since 2001. However, a growing number of sensor applications necessitate wireless operation, and, therefore, impose significant constraints on the acquisition and processing subsystems, which interface to these sensors. The goal of this...
In this paper, we propose an adaptable-order single-loop digital DeltaSigma modulator which offers flexible noise shaping performance to maximize hardware sharing and power efficiency in multi-band frequency synthesizer applications. The proposed architecture utilizes feedback coefficients that allow computationally efficient digital implementation and also yield good noise shaping. Fixed-magnitude...
In this paper, we propose an implementation for digital delta-sigma modulators named as threshold direct synthesis structure. The proposed configuration increases modulator throughput by decomposing a delta-sigma loop into two events, which can be completed in one input clock period. A third-order single-loop digital modulator is implemented using this method and an output/input rate ratio of 1:1...
We propose an analog CMOS image sensor with 10X faster readout settling time than standard active pixel sensor (APS) designs. The pixel in the proposed design is a standard APS source follower configuration thus retaining high fill factor. Negative feedback is applied to the readout of the pixel from a column shared circuit to increase its current driving capabilities and thereby reduce the settling...
In this paper, we present a method to reduce the effects of substrate noise on bandpass sigma-delta (SigmaDelta) ADCs through the use of band-stop noise modulation, where the notch of the modulation noise spectrum is centered around the input signal band. Several band-stop noise (BSN) resonator structures required for bandpass SigmaDelta ADC implementations are presented. The proposed designs have...
We describe a CMOS image sensor employing pixel-level SigmaDelta analog to digital conversion. The design has high fill factor (31%), zero DC offset fixed pattern noise and reduced reset and transistor readout noise in comparison to other analog and digital imager readout techniques. The SigmaDelta pixel design also has low power consumption: 0.88 nW/pixel at 30 fps, high dynamic range of 16 bits,...
We present a pseudo-two-path bandpass sigma-delta (SigmaDelta) modulator design that improves upon current designs by completely suppressing the mirror image in the input signal band. The proposed SigmaDelta modulator structure introduces a resonator consisting of four total paths that are selected in a blue-noise manner, which serves to spread the mirror image caused from path mismatch across the...
In this paper, we propose a method to implement the randomization selection sequence in a time-interleaved (TI) ADC system. The proposed randomization sequence generator is one with blue noise spectral characteristics (high-frequency noise). This selection method guarantees that each individual channel would be selected with the lowest possible rate in order to maintain low speed requirements while...
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