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This paper optimizes the design of an OTA for a Switched Capacitor (SC) Integrator in a discrete time Sigma-Delta Modulator based on the total settling time requirement and by application of the gm /Id method. One of the main constraints when implementing SC Sigma-Delta ADCs for high sampling rates is the requirement for the transition frequency and settling behavior of the operational transconductance...
This paper summarizes the research work carried out during a doctorate studies, which is focused on the synthesis and design of a 4th Order ΣΔ Modulator in Discrete Time (DT) implemented in a 130nm CMOS process. By means of SIMSIDES the high-level simulation of the modulator is analyzed in order to translate the design specifications into a set of values such that the transistor level blocks be established...
This paper presents the analysis of a new implementation for designing a downsampling multirate hybrid Continuous-time (CT)/discrete-time (DT) cascade ΣΔ modulator that saves silicon area and offers a reduction of power consumption. Since the hybrid CT/DT cascade modulator has to be integrated in a standard Integrated Circuit (IC) technology, the analysis problem is formulated as a fast operation...
In this paper SIMSIDES-based (Simulink-based Sigma Delta Simulator) high level simulation of a 4th order Hybrid ΣΔ Modulator was carried out to find the performance requirements of several Analog Building Blocks (ABB). Once the requirements have been defined, the next step is to design each ABB at the transistor level. One of them, a fully differential OTA, was sized through a Design of Experiments...
This paper presents a methodology to design voltage controlled oscillators. The usefulness of the design proposal is shown by designing a LC oscillator in a 130nm CMOS technology, intended for Bluetooth/Zigbee applications. From simulations results, when temperature varies from 0 to 100°C, power consumption ranging from 3.1mW to 3.81mW is achieved. At 3.4mW of power consumption, a phase noise of −119...
This work presents a CMOS compatible method to develop suspended inductors. In other words, if analytical models for designing planar inductors do not take into account unwanted effects (due to the silicon substrate), our proposal is to etch the substrate in order to match both numerical results and experimental data. The accuracy in the inductance value is required not only to develop a design model,...
This modulator, a cascade hybrid proposal, takes advantage of both Continuous Time (CT) and Discrete Time (DT) approaches. In order to define a set of specifications Processing Basic-Blocks (PBBs) are firstly analyzed with the help of SIMSIDES. After that transistor-based simulations are carried out not only to verify fulfil specifications, but also to analyse the effect of non-idealities on the modulator...
Hybrid ΣΔ modulator has the property of take advantage of the capabilities of CT and DT architectures and is thus very effective in the cascade approach. In this paper, we show the behavioral simulation of ΣΔ modulators in SIMSIDES. A set of experiments based on models for analyzing the overall performance of SC ΣΔ modulators were used in order to translate design considerations into a set of values...
The aim of this contribution is to show why sources of non-idealities are actually a concept of reason in order to define tradeoffs in the design of analog circuits. A tradeoff is commonly picked up from an analytical design-model, which tries to explain a given phenomenon under study by using physical theories underlying the role of non-idealities in the design of accurate analog-circuits. Since...
The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5mum CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply...
This paper reviews the main circuit strategies reported so far for the implementation of multi-standard low-noise amplifiers (LNAs) and presents a reconfigurable and adaptive LNA intended for beyond-3G RF hand-held devices. The circuit, designed and implemented in a 90-nm CMOS technology, combines a reduced number of inductors with PMOS-varactors and programmable load to adapt its performance to different...
This paper describes the design of a CMOS double-balanced mixer for UHF applications. The mixer has been designed according technological design rules of a 0.5 mum, N-well CMOS process. Since this design uses 4-transistors per current-branch, operating under the strong inversion regimen, the minimum power supply required for correct operation is 4.8 V. In practice, the mixer's power supply will be...
This paper presents experimental results of a DC-DC converter based on the SC approach. In this design to power digital circuitry a 1.5 V voltage source has been used to emulate the energy to be supplied by a single battery. The voltage source is useful also to start the times2 operation. In order to operate in a correct way the MOS switches a boost circuit based on a single NMOS gain stage was also...
This paper presents the design of a low-power demodulator for RFID applications based on a low-current twice differential amplifier structure. The demodulator, which is an academic project, has been designed according to the technological design rules of a standard 0.5 mum, N-well CMOS process. The demodulator power supply would be taken from the RF energy with help of a voltage multiplier. From simulations...
This paper presents a 1.8-V, 0.18 μm CMOS reconfigurable switched-current ΣΔ modulator for multistandard (GSM, Bluetooth, WCDMA) telecom systems. The modulator topology is an expandable cascade architecture which can be reconfigured both at the architecture level and at the circuit level in order to adapt the modulator performance to the different standards with adjustable power consumption. For this...
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