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This paper presents a new method for the design, modelling and optimization of a uniform serpentine meander based MEMS shunt capacitive switch with perforation on upper beam. The new approach is proposed to improve the Pull-in Voltage performance in a MEMS switch. First a new analytical model of the Pull-in Voltage is proposed using the modified Mejis-Fokkema capacitance model taking care of the nonlinear...
A Low Voltage, Low Power, Low Noise and High Gain Two Stage OpAmp configuration utilizing self-cascoding transistors has been proposed. Self cascoding helps in decrease of Channel Length Modulation Effect and aides in accomplishing high output impedance and output voltage swing, thereby improving the gain. The frequency response of the proposed design makes it conceivable to be utilized as a part...
In emulating biological feature of attention shift, a high slew rate CMOS Winner-Take-Circuit is designed. Particle Swarm optimization has been used in order to optimized multi-objective circuit parameters. Simulation is carried out in MATLAB and CADENCE software. Simulation results demonstrate circuit possesses high slew rate (around 400V/µs) and facilitate attention shift
In the VLSI Physical Design Stage, Floorplanning is an essential step, as it is an effective means to manage circuit design complexity, which is increasing with the advancement in technology. Floorplanning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout. Computationally,...
This paper discusses the Elmore delay optimization technique by varying the wire width. It also throws a light on various aspects which affects the interconnect delay. We will see that the delay minimization to zero will lead to a larger area covering interconnect wires, which will ultimately increase the area cost of IC. So 10 to 15% delay will give a good result keeping the IC size also in control...
In this paper we employed Winner Take All (WTA) circuit for sensing the bit line capacitance. It is an important block in hardware realization of neural networks. The property of a neural logic of selection of the highest intensity signal amongst competing signals highly fits for our design of amplifying the voltage difference between bit lines quickly. A comparative study is done to show the better...
In this paper we present the design and analysis of a fully integrated CMOS low noise amplifier (LNA) in .18 um CMOS technology with operating frequency of 2.4 GHz. Employing a Forward body biasing scheme with cascode configuration ultralow power consumption of 0.15 mW is obtained with an ultra low supply voltage of 0.5 V. The effect of the output matching network on stability has been shown by using...
The design and simulation of a novel CMOS voltage mode WTA (winner-take-all) circuit is described. The circuit employs additional inhibitory and local excitatory feedback based on a common voltage computation and this improves both speed and precision drastically. As a result, a single stage cell provides better resolution in comparison to previous works where cascading of multiple stages is necessary...
The design and simulation of a novel CMOS voltage mode LTA (loser-take-all) circuit is described. The circuit employs additional inhibitory and local excitatory feedback based on a common voltage computation and this improves both speed and precision drastically. As a result, a single stage cell provides better resolution in comparison to previous works where cascading of multiple stages is necessary...
The design of a high speed packet switch has been described here. The switch having 4 inputs and 4 outputs (4 ?? 4) each of four inputs is further subdivided into additional four input queues. The proposed designed have considered both restricted sharing as well as complete sharing. In restricted sharing a finite threshold is imposed to all queue's length. However on unrestricted sharing one queue...
The design and simulation of a novel CMOS voltage mode parallel circuit is described. The circuit employs additional inhibitory and local excitory feedback based on a common voltage computation and this improves both speed and precision drastically. As a result, a single stage cell provides better resolution and speed in comparison to previous works. where cascading is necessary in to improve resolution...
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