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Manufacturable processes to reduce both channel and external resistances (RExt) in CMOS devices are described. Simulations show that RExt will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiNx liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug...
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