The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Physics-based compact modeling, supported by numerical simulations, is used to show the significance of "drain-induced charge enhancement" (DICE) in nanoscale double-gate (DG) MOSFETs. DICE, which is the strong-inversion counterpart of drain-induced barrier lowering (DIBL), is shown to significantly benefit drive current, without affecting the gate capacitance much, and hence can improve...
In this paper we calibrate our process/physics-based DG MOSFET model (UFDG (Fossum, et. al., 2004)) to contemporary DG FinFETs, and examine carrier mobilities in the undoped UTBs. The calibrated model is also used to give interesting insights on carrier transport in nanoscale DG FinFETs that contradict ITRS projections
The ITFET is novel device architecture; it offers significant advantages over planar and FinFET technologies. The ITFET uses traditional CMOS processing technologies and can be rapidly inserted into existing SOI process flows. Doped channel ITFET devices have been demonstrated future work will include undoped channel ITFET devices. Simulated performances of the ITFET devices predict these devices...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.