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As interconnect delay is tremendously increasing in DSM era, placement can greatly affect the throughput of a sequential cyclic system. In this paper, we propose a throughput-driven hierarchical partition-based placement algorithm targeting two-dimensional regular multicycle communication architecture named regular distributed register architecture. Our algorithm adopts a refined quadrisection-based...
NAND flash memory is one of the most important components in modern non-volatile storage media. However, long command setup time and slow I/O interface frequency of current NAND flash device has been limiting the bandwidth of data transfer. In this paper, we propose a high-performance NAND flash controller architecture by exploiting two techniques - parallel out-of-order execution of multi-die commands...
In this paper, we exploit the concept of sequential way access to reduce the number of ways being activated on each access of set-associative cache for low energy consumption while maintaining performance. The proposed architecture accesses each way in sequence, and then eliminates subsequent accesses if a hit is detected. It features smart cache placement and replacement policies to minimize the...
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