The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Block Turbo-codes (BTC) are promising forward error correction (FEC) codes providing close-to-optimal coding gain for rather high coding rate ( R > 0.7) and less subject to an error floor than Convolution Turbo Codes (CTC). Due to its good convergence properties, the Fang-Buda algorithm (FBA) allows efficiently decoding BTC in far less iterations than traditional soft-decoding...
This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain...
A pulse equalizer for hard disk systems is presented. Opposed to classical realizations it is full CMOS while operating at 50 MHz cut-off frequency. For pulse slimming, the equalizer is capable of 13 dB selective boost around the cut-off frequency. The equalizer is a gm-C, seventh order 0.05?? equiripple-on-the-phase low pass filter. It is made out of highly symmetrical biquads with elementary OTAs...
A phase detector for timing recovery phase locked loops with an accuracy better than 0.5 % for input frequencies up to 100 MHz is presented. The core of the phase detector consists of two modified Gilbert cells combined so that the offset in their output current is cancelled. This core is expanded with logic circuitry at the input to make the phase detector suitable for timing recovery applications...
In this paper a CMOS alternative amplitude detection system is presented. It is designed as an alternative for the, bipolar, amplitude detection in hard disk systems. The amplitude is detected by converting the input voltage to a current, rectifying the current, and integrating it on a capacitor. For this a new OTA topology and a rectifier cell are designed. This circuitry is expanded with a very...
An open system for EIT reconstruction algorithms is proposed. It runs under a Windows 3.0 environment on a PC, with a 80386 and a mathematical coprocessor. The fundamental core is a collection of conventional one-step or iterative algorithms. Research results have allowed a trade-off between accuracy and computation speed. Several image enhancement tools are also provided.
A voltage driven EIT system is discussed capable of imaging at high voltage frequencies. This system makes no use of current sources to inject the current and no common mode feedback is implemented. However, experiments have shown that the sampled data compared to simulated data does not show a large systematic error (less than 2% for 12 bit ADC's).
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.