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A Baseband Digital Predistorter design is proposed in this paper for a UHF 8 MHz Power Amplifier (PA) for DVB-T transmitter. A Memory Polynomial (MP) model is considered for the PA characterization and its coefficients are estimated based on Least Square Estimation (LSE) algorithm. The Indirect Learning Architecture (ILA) approach is used to estimate the coefficients of the predistorter. Simulation...
A new DAC behavioral model for system-level simulations is introduced. After presenting the most critical DAC parameters, the proposed modeling technique is described. It takes into account both the static and dynamic limitations of the DAC component while being close the circuit architecture. The impacts of the DAC dynamic impairments are then studied at the system-level for the WirelessHD standard...
This paper proposes the design of a tri-band AIS1, AIS2 and DSC VHF receiver. Original highly integrated and single path RF front-end is defined by replacing conventional analog mixers with a sample and hold circuit for frequency downconversion. Detailed system level design based on RF-subsampling theory allowed the choice of an optimized sampling frequency of 48.93 MHz for the three radio bands by...
This paper presents a novel subsampling-based down-conversion topology for multistandard radio receiver design. This receiver topology is based on two subsampling stages. The first stage has a fixed RF subsampling frequency; however, the IF sampling frequency of the second stage is variable and depends on the standard being considered. This approach overcomes various undesirable effects related to...
In this paper, two track and hold circuits are designed and implemented using 65 nm CMOS technology. The first circuit is based on a dummy switch topology to decrease the charge injection error. The second circuit uses a clock linearization technique to reduce the sampling instant inaccuracy. Simulation results show that the track and hold circuit based on dummy transistor technique presents the best...
Sampling-based downconversion architecture was proposed in (R. Barrak et al., 2007) for multistandard RF subsampling receiver. By an appropriate choice of RF and IF subsampling frequencies complete multistandard RF bands are downconverted to baseband. This paper presents a reconfigurable discrete-time switched capacitor filter at the baseband stage which serves as an anti-aliasing and a decimation...
This paper presents an optimized design of an AIS/DSC homodyne receiver for maritime applications. Several receiver architectures are investigated and the optimal one in terms of noise figure and complexity is selected. AIS/DSC receiver is designed based on commercially available parts. The receiver's performance is found to meet the specifications through ADS simulations using commercial parts' properties...
This paper presents an improved sampling-based downconversion topology design for multi-standard RF subsampling receiver. Wideband RF receiver architecture is proposed for multimode processing with high-level integration. By an appropriate choice of subsampling frequency complete multistandard RF bands are downconverted to IF domain. Baseband downconversion is achieved by a second subsampling stage...
This paper presents an improved sampling-based down conversion topology design with double RF filters for multi-standard RF subsampling receiver. Proposed architecture is limiting down conversion to IF domain and adding a first tunable RF filter to select multistandard RF bands. To overcome subsampling negative effects on receiver performances a second RF filter is inserted before subsampling operation...
This paper presents an improved topology design at RF system architecture level for multi-standard radio receiver based on RF subsampling technique. By limiting downconversion to IF domain, a single path for RF signal analogue processing is used avoiding circuit complexities and allowing software-based IF processing in DSP stage. This ensures required configurability for multimode operation with high-level...
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