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With the use of non-tree topology in signal nets, the delay issue in non-tree topologies has become an important problem. In this paper, based on the transformation-based timing analysis for a non-tree interconnection, an iterative wire-sizing approach is proposed to assign feasible widths onto the wire segments to minimize the timing delay in the critical path for a non-tree interconnection under...
Given a set of connecting nodes in a signal net with a set of obstacles on different layers for 3D ICs, based on the refinement of minimum routing region and the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree with obstacle avoidance. Compared with a spanning-tree-based approach,...
In this paper, given a set of n terminals including some current sources and some current sinks in a signal net, the maximum current density and the minimum wire width, a current-driven routing tree can be constructed to satisfy the current flow in Kirchhoffpsilas current laws. Furthermore, all the area-driven Steiner points are assigned to reduce the total wiring area based on the determination of...
In this paper, based on the equivalent circuit of on-track or off-track redundant via insertion and the timing delay of each net in as the timing constraint, an enhanced timing-constrained two-phase insertion approach for yield optimization is proposed to insert on-track and off-track redundant vias. For the Poisson yield model in redundant via insertion, the experimental results show that our proposed...
Given a set of connecting nodes in a signal net on different layers for 3D ICs, based on the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree. Compared with a spanning-tree-based approach, the experimental results show that our proposed approach has 9.7%~16% improvement in...
Given a routing panel, the routability-driven ordering and location constraints can be firstly set according to the pin positions of all the wire segments in the panel Based on routability-driven ordering and location constraints in the panel, an ASAP-based scheduling approach with efficient space insertion is further proposed to reduce total coupling capacitance for routability-driven track routing...
In this paper, given a set of connecting nodes in a signal net, based on the result of optimal wire width and buffer insertion in a wire segment (Yan, 2006) and the concept of sharing-buffer insertion and hidden Steiner-point assignment, an effective tree construction approach is proposed to construct a timing-driven rectilinear Steiner tree with wire sizing, buffer insertion and obstacle avoidance...
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