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Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such...
This paper describes electrical, optical, and fluidic (or 'trimodal') chip I/O interconnect networks for gigascale systems to meet and exceed end-of-roadmap projections in the areas of power delivery, off-chip bandwidth, and heat removal, respectively. The trimodal I/O technology is proposed to overcome the adverse effects of conventional silicon ancillary technologies on the performance of a gigascale...
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