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Switching noise generated by digital circuits can degrade analog circuit performance in mixed-signal integrated circuits (ICs). In an analog-to-digital converter (ADC), one major source of switching noise is digital output drivers. Traditional methods for mitigating this problem mostly have been to isolate the analog and digital circuits to minimize digital noise coupling into sensitive analog nodes...
While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a critical limit. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. The floating-body 1T-DRAM takes advantage of floating-body and coupling effects that...
We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 µm2 (Fig. 1). The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node [1]. A trigate device architecture with a minimum contacted gate pitch (CGP) and minimum contacted fin pitch (CFP) of 50...
FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed...
We present an aggressively scaled trigate device architecture with undoped channels, high-k gate dielectric, a single work function metal gate and novel BEOL processing yielding 6T SRAM bit cells as small as 0.06 μm2. This is the smallest SRAM cell demonstrated to date and represents the first time an SRAM based on a multi-gate FET (MUGFET) architecture has surpassed SRAM density scaling demonstrated...
We demonstrate 22 nm node technology compatible, fully functional 0.1 mum2 6T-SRAM cell using high-NA immersion lithography and state-of-the-art 300 mm tooling. The cell exhibits a static noise margin (SNM) of 220 mV at Vdd=0.9 V. We also present a 0.09 mum2 cell with SNM of 160 mV at Vdd=0.9 V demonstrating the scalability of the design with the same layout. This is the world's smallest 6T-SRAM cell...
Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell,...
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