The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper shows how floating gate memory cells behavior during retention tests can be predicted relying on static stress tests. The electric high-field induced during write/erase cycles is mainly responsible for the retention time degradation because it creates intrinsic failures or traps in the EEPROM tunnel oxide.
To ensure reliability of EEPROM devices, it is significant to monitor the evolution of the memory array threshold voltage (VT) distribution. In this work, impact of endurance and retention tests is evaluated on EEPROM VT distributions. To track accurately the evolution of the VT distribution, an innovative experimental plan is setup and experimental results are deeply analyzed.
The objective of this paper is to present a flash EEPROM memory diagnosis methodology based on I-V cell characteristics extraction. In this work, the root cause of any variation of the memory cell IN characteristic is investigated. Thus, this method allows to quickly diagnose any variation of the memory IN shape in terms of design parameters, process variability, electrical variations, bridge and...
The fundamental discussion of this paper is to show the influence of peripheral circuits' marginalities, like reading and programming circuitry, on the threshold voltage (Vth) distributions of an EEPROM memory array. The initial Vth dispersion induced by peripheral circuits' is tracked during cycling/retention test. To understand Vth distribution variation within the memory array, simulations are...
The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example...
This paper presents an efficient technique to decrease simulation lime of EEPROM memory arrays. This technique is based on the complexity reduction of an existing compact EEPROM model. This original model is unsuitable when dealing with large memory arrays simulations. To overcome this limitation, the authors propose two alternative models which allow reducing time and memory space overheads when...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.