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The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient delay modeling of interconnection is needed for high speed ICpsilas. This paper presents a closed-form expressions for RLC interconnection trees in current mode signaling, which can be implemented in VLSI design tool. These analytical model expressions can be used for accurate calculation...
The demand for powerful computational machines using scaled technologies has brought power dissipation to the forefront. Hence there is a need to accurate model power dissipation in high speed VLSI chips. The power consumption of interconnects has become an important issue as technology scales down. Therefore efficient power modeling of interconnects are necessary where inductance effect is dominant...
Timing driven physical design, synthesis, and optimization tools need efficient closed-form delay models for estimating the delay associated with each net in an integrated circuit (IC) design. The total number of nets in a modern IC design has increased dramatically and exceeded millions. Therefore efficient modeling of interconnection is needed for high speed ICpsilas. This paper presents an closed-form...
This paper presents a comparison between different approaches for fault classification in transmission lines. Fault classification is necessary for reliable and high speed protective relaying followed by digital distance protection. Three Fault classification techniques are presented for comparison in terms of complexity and time. Firstly, based on evaluation of symmetrical components of fault currents,...
Mobile ad hoc networks shows unexpected behavior with multiple data streams under heavy traffic load such as multimedia data when it is sent to common destination. The main reason for packet loss in mobile ad hoc networks is due to congestion. In the current design, the routing protocols are not congestion adaptive. The way in which the congestion is handled results in longer delay and more packet...
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