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The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a...
On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.
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