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In this paper, a 2.5-Gb/s oversampling clock and data recovery (CDR) circuit with frequency calibration is realized for optical communication. The CDR circuit contains a fractional-N phase-locked loop (PLL), a delta-sigma modulator (DSM) and a data recovery circuit. The recovered clock is adjusted by the DSM for phase and frequency tuning, incorporating with the phase detector, when the incoming data...
In this paper, a frequency synthesizer based on phase-locked loop (PLL) technique for dual-mode WiFi (2.4-GHz band) and WiMax (5-GHz band) applications is presented. The frequency synthesizer with wide frequency range application and the settling time within 10-mus is realized by a time-to-voltage converter (TVC). A 40-MHz input reference for 125-KHz frequency steps which is realized by a 12-bits...
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