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Equivalence and dominance relations used earlier in fault diagnosis procedures are defined as relations between faults, similar to the relations used for fault collapsing. Since the basic entity of diagnostic fault simulation and test generation is a fault pair, and not a single fault, we introduce a framework where equivalence and dominance relations are defined for fault pairs. Using equivalence...
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected...
Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number...
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compaction procedure for SAT-based ATPG which utilizes internal data structures of the SAT solver to extract essential fault detection conditions and to generate patterns which cover multiple faults. We complement this technique...
It was shown earlier that simulation of a transition fault under a test may indicate that the fault is detected by the test only if detection conditions referred to as hazard-based detection conditions are considered. The hazard-based detection conditions were applied to fault simulation and test generation for transition faults under scan-based tests. In this case, the increase in fault coverage...
Broadside tests are two-pattern scan-based tests for delay faults. One of the complications that occur in relation to the application of broadside tests from an external tester is the need to change the primary input vector applied to the circuit at-speed during the test. We explore a solution to this problem where the second primary input vector of every test is produced on chip. The important features...
We define the notion of a lingering synchronization effect. Such an effect occurs when a primary input cube (an incompletely-specified primary input vector) determines the state of a circuit for several time units after it is applied. Such a primary input cube may prevent certain faults from being detected when it appears in a test sequence. It should therefore be avoided when the goal is to achieve...
Markov sources have been shown to be efficient pseudo-random pattern generators in SCAN-BIST. In this paper we give a new design for Markov sources. The new design first reduces the ATPG test set by removing the test cubes with low sampling probability and then produces test sequences based on a unique dynamic transition selection technique. Dynamic transition selection offers four transition options...
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the errors in responses due to defects which are captured in scan cells are not directly observed. We propose a simple and effective way to enhance the diagnostic resolution achievable by production tests with minimal increase...
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern...
We describe a preprocessing step to fault diagnosis of an observed response obtained from a faulty chip. In this step, a fault model for diagnosing the observed response is selected. This step allows fault diagnosis to be performed based on a single fault model after identifying the most appropriate one. We describe a specific implementation of this preprocessing step based on what is referred to...
A recent approach to test generation avoids the assignment of certain input values in order not to prevent target faults from being detected. The test generation process based on this approach is efficient; however, it generates large test sets. We develop a dynamic test compaction procedure for this approach. Our goal is to reduce the test set size by increasing the number of faults detected by each...
We consider a class of symmetric Hopfield Networks, with nonpositive synapses and zero thresholds and address a variety of design and analysis issues conected with Unidirectional Error Correcting Coding applications of this class. We show that this class is naturally suited to work in a unidirectional error environment We give a necessary and sufficient condition for a set of vectors to be storable...
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