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Supporting the online debugging is one of the design goals of SoC. Usually the function unit and the debugging structure are tightly coupled, thus it is hard to reuse the debug structure in other systems. This paper presents an on-chip debug method for SoC bus architecture. The system reuses On Chip Bus(OCB) as the transmission path for debugging data and debugs the units in system in form of bus...
This study presents hardware architectures performing correctly rounded Floating-Point (FP) multioperand addition and dot-product computation, both of which are widely used in various fields, such as scientific computing, digital signal processing, and 3D graphic applications. A novel realignment method is proposed to solve the catastrophic cancellation and multi-sticky bits. Only one rounding operation...
Multi-operand adder is one of attractive solutions compared with a network of 2-operand adders for accelerating algorithms including a lot of addition operations. In this paper, an improved 3-operand floating-point (FP) adder has been presented. Firstly, the internal width of the adder has been given which is compatible with IEEE-Std754. Secondly, a realignment method processing sticky bits is used...
Process capability ultimately decides process quality level. Based on analyzing process capability index (PCI), process capability may be effectively assured. For the multivariate manufacturing processes, tremendous difficulties are often encountered when one attempts to measure the process capability by directly extending the univariate approach. The paper presents a modify spatial multivariate PCI...
The task of computing both the summation and difference of a pair of Floating-Point (FP) data is often needed in some Digital Signal Processing (DSP) algorithms and other applications. A basic fused add-subtract unit (FAS) is introduced [1] to perform simultaneously both addition and subtraction operation for a couple of operands and has less hardware overhead than the general approach using two FP...
Dot product computation is widely used in many algorithms, such as FFT and DCT. This paper proposes a floating-point dot product architecture based on the multiple-path method. This architecture could perform A × B+C × D as a single operation. The speed of the dual-path architecture implemented in single precision format is faster by 32% and 5.45% than the speed of a network approach using traditional...
Simulation overhead becomes more decisive for VLSI design cost. A parallel method to accelerate VLSI logic simulation with GPGPU is addressed in this paper. To explore further parallelism and locality of logic simulation, we present an adaptable partition strategy to achieve variable coarse-grain partitioning targets on the GPU platform, which varies with the load balance factor in parallel threads...
With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation scaling. Technology trends such as transistor downsizing, use of new materials and high performance computer architecture continue to increase the sensitivity of systems to soft errors. Today the technologies are moving into the period of nanotechnologies and...
In a partially reconfigurable system with online placement algorithm, we try to avoid mapping some redundant tasks by caching modules on the reconfigurable area. This paper proposes an elaborate strategy named virtual deletion and a low cost board- level hardware named recycle cache to accomplish the goal. In our strategy, the record of corresponding module is deleted from placer and indexed in the...
This paper describes the design of a fully integrated PC-architecture SoC for industrial control which is capable of executing DOS and X86-compatible binary applications. It is a high performance and cost-effective SoC and meets the needs of embedded applications. The SoC provides 2 UARTs, 1 ECP/EPP parallel port, PC104 bus interface, 15 interrupt requests, 3 DMA requests, 3 timers, and 1 watchdog...
The Aviation Microelectronic Center of NPU (Northwestern Polytechnical University) has recently completed the development of a 32-bit super-scalar RISC microprocessor, called "Longtium" R2. In this paper the architecture of "Longtium" R2 is presented. Firstly, the whole architecture of the "Longtium" R2 microprocessor is presented. Gives the schematic diagram of the architecture...
With the development of the modern architecture and chip integration technology, parallel process technologies have become the mainstream. The increasingly large gap between processor and memory speed has made the design of high bandwidth and large scale cache a key part in high performance microprocessor. In this paper, we describe the design of a 16-port data cache, which is 8-way associative using...
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