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Detailed routing is an important stage in VLSI physical design. Due to the high routing complexity, it is difficult for existing routing methods to guarantee total completion without design rule checking violations (DRCs) and it generally takes several days for designers to fix remaining DRC-s. Studies has shown that the low routing quality partly results from non-optimal net-ordering nature of traditional...
Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional works that handle this problem with clock routing or buffer sizing, this paper proposes a novel register clustering algorithm in generating...
As complexity of VLSI circuits grows, routability has been one of the key factors considered by tree construction algorithms in global routing. Flexibility is a geometric structural property of rectilinear Steiner minimal tree (RSMT), and it is expected to accord with routability and therefore predict the overflow situation. Reference [9] proposed a new definition of flexibility of RSMT, combining...
As a key phase of force-directed placement, cell spreading can smooth the overlap linearly by adding additional forces to shift cells to the suitable place based on the utilization of bins. However, the magnitude and direction of these additional forces is hard to be determined. Unreasonable additional forces will bring great damage to the wire length and run time. In this paper, we present a new...
As a key phase of force-directed placement, cell spreading can smooth the overlap linearly by adding additional forces to shift cells to the suitable place based on the utilization of bins. However, the magnitude and direction of these additional forces is hard to be determined. Unreasonable additional forces will bring great damage to the wire length and run time. In this paper, we present a new...
Transient analysis is the most practical and effective approach for power grid validation, but which is very chal-lengeable for large scale VLSI chips because it is really time consuming and requires large memory resources. In this paper we proposed a parallel transient simulation approach for efficient power grid analysis. Firstly we adopt symmetric formulation for NA equation of RLC power grid to...
This paper proposes an efficient decoupling (decaps) capacitance optimization algorithm to reduce the voltage noise of on-chip power grid networks. The new method is based on the efficient charge formulation of the decap allocation problem. But different from the existing work [12], the new method applies the more accurate piecewise polynomial micromodels to estimate the voltage noises during the...
In this paper, we propose a novel simulation algorithm for large scale structured power grid networks. The new method formulates the traditional linear system as a special two-dimension Poisson equation and solves it using an analytical expressions based on FFT technique. The computation complexity of the new algorithm is O(NlgN), which is much smaller than the traditional solver's complexity O(N1.5...
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