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In this paper we present the Acquisition Speed Up Engine (ACSE) algorithm, devised in 2007 by Thales Alenia Space in the framework of studies for the GIRASOLE receiver and implemented by Consorzio Pisa Ricerche. The algorithm is used to fast detect the presence of a CDMA signal in a time/frequency uncertainty domain. This is made possible with a serial/parallel approach and a modified FFT algorithm...
This paper deals with the design of a processor for very-finely spaced spectral analysis over a narrow band of the available spectrum. The processor implements the chirp z-transform (CZT) algorithm, and exploits a fully-parallel architecture in order to address real-time applications with very-high throughput. The internal data-path is optimized as a trade-off between fixed-point accuracy and implementation...
This paper describes the architecture of a flexible and reconfigurable processor for the computation of the state-metric recursion in a multi-standard BCJR decoder. The unit can serve binary as well as duo-binary codes with any number of states. The architecture is arranged into a cluster of state-metric processors plus two multiplexing networks for feedback and normalization, configured on-the-fly...
A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative message passing (iMP) to be run on loopy graph. This technique approximates the maximum-likelihood (ML) estimator, providing a sub-optimal algorithm that searches all possible code phases in parallel, at low complexity and fast acquisition time. This work is addressed...
Low-density parity-check (LDPC) codes have recently been included as error-correcting codes in IEEE 802.16e, for wireless metropolitan area networks. This paper proposes a flexible, low-complexity LDPC decoder fully compliant with all 114 codes defined by the standard. The decoder runs the layered decoding algorithm to increase the convergence speed, and relies on a semi-parallel implementation with...
This paper describes the application of a new hardware architecture to the design of a decoder for low-density parity-check (LDPC) codes. Thanks to the systematic use of the built-in stopping rule in the decoder, the decoder runs the minimum number of iterations on each packet of received data. The addition of a small buffer on the decoder input allows the exploitation of the variations in the decoding...
This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards. A complete exploration of the design space spanning from the decoding schedules, the node processing approximations up to the top-level decoder architecture is detailed. According to this search state-of-the-art techniques for a low complexity design...
The need for circularly shifting an array of data is a distinguishing feature of decoders for structured low-density parity-check (LDPC) code, as a result of an efficient trade-off between performance and parallelisation of the elaborations, or throughput. Since the decoder must typically cope with blocks of data with different size, described is an efficient architecture of a reconfigurable multi-size...
This paper describes the design activity for the digital baseband processing of a prototype receiver for the Galileo system. According to the applied hardware-software partitioning, the high rate elaborations have been implemented on a dedicated hardware, a Xilinx Virtex2 FPGA, while the remaining low rate processing has been programmed on an analog device DSP. A customarily designed prototype board...
The principle of "layered decoding" is extended to those codes not especially conceived for this practice, as to benefit of the increased convergence speed. Two different strategies are considered to solve the problem and the related architectures presented: one more straightforward, and based on the use for the soft output of the last value originated in a layer; the other based on the...
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