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Dynamic random access memory (DRAM) is one key component in modern electronic systems. In this paper, we propose a software-hardware-cooperated built-in self-test (SHC-BIST) scheme for the channel-based DRAMs. The testing of DRAMs consists of two major phases: DRAM initialization and DRAM array testing. Typically, the DRAM initialization process is short and executed in the beginning of the DRAM array...
A DRAM with multiple-refresh-period (MRP) method is one of effective refresh power reduction techniques. To support the MRP method, effective test methods for classifying the refresh period of each DRAM block are needed. In this paper, we propose an effective test method for classifying the refresh periods of DRAM blocks. Also, a programmable built-in self-test (BIST) scheme being able to support...
With the shrinking of technology node, the data retention time of DRAM (DRAM) cells is widespread. Thus, the number of the cells with data retention faults is increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies with physical and logical reconfiguration mechanisms. Spare rows and columns with physical reconfiguration mechanism are used to...
Memristor is a resistive device which is considered as an alternative non-volatile device for future non-volatile memories. For a memristor memory, a reference current is needed for discriminating the high-resistance (ROFF) state from low-resistance (RON) state. The reference current has an impact on the yield and reliability of the memristor memory. In this paper, we propose a test method in associate...
This paper proposes a built-in delay measurement (BIDM) technique to measure the delay of through-silicon via (TSV) in the phase of post-bond test. The BIDM circuit can be shared by multiple TSVs such that the area overhead of the BIDM circuit is minimized. Furthermore, a measurement flow is proposed to eliminate the delay of interconnection between two TSVs such that the BIDM accuracy is not worsened...
In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast...
Wide-I/O dynamic random access memory (wide I/O DRAM) is one of promising solutions to increase the memory bandwidth. Similar to modern double-data-rate DRAMs, the minimum burst length of wide I/O DRAM is at least two. Thus, either a read or a write operation is executed, two words will be read or written at least each time. This causes that the testing of inter-word coupling faults becomes complicated...
Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two...
This paper proposes a hybrid BIST scheme for DRAMs. The hybrid BIST consists of a microcode-based controller to support the programmability of test algorithms and an FSM-based controller to support the in-field programmability of configuration parameters of the DRAMs. Thus, if the needed test algorithms are out of the test algorithms stored in the microcodes, only metal changing is needed to change...
An non-volatile logic (NVL) -based system chip uses non-volatile storage elements to backup working state of volatile storage elements in sleep mode such that the power of chip can be turned off and zero standby power can be achieved. Since an NVL-based system chip consists of logic circuits and non-volatile storage elements, tests for logic circuits only and for non-volatile memories only are not...
Three-dimensional dynamic random access memory (3D DRAM) using through-silicon via (TSV) has been acknowledged as one good approach for overcoming the memory wall. However, the IO-channel power of a TSV-based 3D DRAM represents a significant portion of the 3D DRAM power. In this paper, we propose a built-in self-test (BIST) -assisted tuning scheme to adjust the driving capability of programmable drivers...
Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro...
Contests and their benchmarks have become an important driving force to push our EDA domain forward in different areas lately, such as ISPD, TAU, DAC contests. The annual CAD Contest in Taiwan has been held for 14 consecutive years and has successfully boosted the EDA research momentum in Taiwan. To encourage better research development on timely and practical EDA problems across all domains, CAD...
NAND flash memory is the most popular nonvolatile memory. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot, some...
Three-dimensional (3-D) integration technology using through-silicon via (TSV) is an emerging integrated-circuit (IC) design technology. In this paper, we propose a repair scheme to enhance the yield of TSVs in 3-D ICs. The proposed TSV repair scheme uses an enhanced test access architecture to alleviate the requirement of additional repair registers such that the area cost can be drastically reduced...
Data retention time distribution of a dynamic random access memory (DRAM) has a heavy impact on its yield, power, and performance. Accurate and detailed information of data retention time distribution thus is very important for the DRAM designer and user. This paper proposes an FPGA-based test platform for analyzing the data retention time distribution of a DRAM. Based on the test platform, a test...
Three-dimensional (3D) integration using through silicon via (TSV) is a promising approach to coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented by stacking multiple dies which are vertically connected by TSVs. This may shorten the global interconnects of a 3D IC and greatly improve its performance and power consumption. High bandwidth is achieved by the...
Dynamic random access memory (DRAM) is one key component in handheld devices. It typically consumes significant portion of the energy of the device even if the device is in standby mode due to the refresh requirement. This paper proposes a hybrid error-correcting code (ECC) and redundancy (HEAR) technique to reduce the refresh power of DRAMs in standby mode. The HEAR circuit consists of a Bose-Chaudhuri-Hocquenghem...
A modern system-on-chip (SOC) may become one of the dies of a three-dimensional (3D) IC using through-silicon via (TSV). Built-in self-repair (BISR) techniques have been widely used to improve the yield of RAMs in a SOC. This paper proposes a memory BISR allocation scheme to allocate shared BISR circuits for RAMs in a SOC die such that the test and repair time and the area of BISR circuits are minimized...
Three-dimensional (3D) random access memory (RAM) using through-silicon vias for inter-die interconnects has been considered as a new approach to overcome the memory wall. In this paper, we propose a built-in self-test (BIST) scheme for 3D RAMs. In the BIST scheme, a clock-domain-crossing-aware test pattern generator is proposed to cope with the clock-domain-crossing issue. An inter-die synchronization...
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