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This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from pre- and background-calibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for fractional operation is proposed to lower...
This paper presents a 7.9 fJ/conversion-step 10-bit 125 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) on the basis of a monotonic capacitor switching procedure. Simplified power-efficient digital control logic, multi-layer sandwich capacitor structure and high-speed level-shift bootstrapped sampling-and-holding (S/H) blocks are employed to achieve high performance...
This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages...
This paper presents a 0.5–2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rd harmonic rejection...
This paper presents a SAW-less 0.2–3GHz front-end with high out-of-band linearity. Modified impedance translation technique based on N-path current driven mixer is used to improve out-of-band IIP3. At the input node, an 8-path passive mixer switched by 8-phase clocks at the frequency of ƒLO/2 is utilized to achieve impedance match at ƒLO and filter out-of-band interferes, while contribute negligible...
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