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This paper applies for the first time an RF equivalent of the four-point probe Kelvin DC technique to characterize the TSV inductance. This RF approach is based on two-port S-parameter measurements over a wide frequency range using a vector network analyzer (VNA). The approach is easy to implement to determine the TSV inductance, which can be complementary to the DC Kelvin measurements. In addition,...
We investigated the impact of oxide liner elastic modulus and thickness on through-silicon via (TSV) Cu pumping and stress. A low-k dielectric liner showed a decrease in residual Cu pumping and TSV stress compared to O3-TEOS SiO2 and ALD SiO2 liners. For TSVs with a post-plating anneal, residual Cu pumping decreases from (102 ± 7) nm to (11 ± 1) nm (99.9th percentile) when the O3-TEOS SiO2 liner thickness...
Through 3D-IC Integration is possible to put more transistors on the same footprint without the need to shrink transistor sizes. As for any new technology, there are many challenges and issues that need to be addressed before moving to high volume manufacturing. In this work we introduce the several processes to generate 3D stacked devices. We focus on processes like TSV, wafer thinning, backside...
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