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A 2-read/write dual-port SRAM and 1-read/1-write two-port SRAM with stable operation at temperatures of −40 to 170°C are implemented in 40 nm embedded flash CMOS technology for automotive microcontroller applications. To reduce the leakage current and to ensure the read/write operating margin at over 125°C, a new 8T SRAM bitcell with the optimized process and sizing is proposed. A test circuit for...
We propose a partially write-assisted two read/write dual-port (DP) SRAM in 28-nm technology. Our write-assist circuit with metal-coupled capacitance can generate negative bitline bias which is flexibly adjustable to any bit-word configurations. By effectively applying assist biases only to sub-blocks with margin-less bits, power overhead can be reduced with Vmin improved. A test chip including proposed...
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