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Power consumption during testing is becoming a primary concern. In this paper, an adjustable clock scan structure is presented. It can significantly reduce the peak power consumption during testing. The adjustable clock controlling multiple scan chains is used to reduce SA (switching activity) and avoid simultaneous shifting operation. Compared with exiting techniques of low power scan testing, the...
With the rapid development of IC design methods and manufacturing technologies, the scale of IC is becoming lager and lager, and the design method of system on chip (SoC) has been widely adopted. In the design process of SoC, the test problem is viewed as the bottleneck of the SoC development; and it is a challenge to test the IP (intellectual property) cores which are embedded deeply in the SoC especially...
Along with the development of the multi-core system, the testability of circuit faces many new challenges. Relay wave propagation test of arrays (RWPA) has many advantages in single-chain and multi-chain boundary scan (BS) circuit. In this paper, the improved single-chain RWPA is tentatively applied to the multi-core BS architecture, to reduce the test time and increase the fault coverage. As an experiment,...
With the increasing complexity and chip scale of SoC, the test problem is becoming more difficult and important. Adding DFT (design for testability) in SoC design period has become the main method for solving the test problem. Based on analyzing some common DFT structures such as Fscan-Bscan, Fscan-Tbus, and the standard for embedded core test (SECT) IEEE P1500, a system-level mixed DFT-TAM (test...
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