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Management innovation is the key element for an enterprise's sustainable development, which determines whether an enterprise can stand out in the fierce competition of 21st century, and develop rapidly so as to keep an enterprise sustainable running. Through empirical research on innovative management of Delixi-electric Co.Ltd, a Sino-French joint venture, this article summarizes the practice of the...
Bidders at the tendering stage conceal the existence qualifications, reputation, management level, financial status and so on, which brings a potential danger to the smooth implementation of projects and contract goals, and the bidder's unbalance bidding based on the tendering document's flaw, using itself construction technology or management advantages , the future of the project expected and so...
This paper proposes a scheduling method of SOC (System on Chip) interconnect test complied with IEEE Std 1500 based on Genetic Algorithm. The algorithm figures out optimal scheduling of interconnect test for high utility of TAM (Test Access Mechanism) width, and eight fixed test patterns are used to cover static and Signal Integrity faults based on MA (Maximum Aggressor faults model) for specific...
This paper presents a combinational test generation method for transition faults in acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit is performed on its extend time-expansion model. The model is composed of two copies of time-expansion model of the given circuit and extends in the close two sequences to generate 2 vectors...
Shrinks of feature size, high working frequency, and rising number of the IP cores integrated in SOC make the problem with interconnection test critics. A March-CL test for interconnection faults of SOC is proposed in this article. According to the method, eight test patterns are used to detect stuck and delay faults of interconnection between IP cores. The IP connected by interconnection under test...
Both wrapper and TAM are important components in SOC test architecture, and wrapper scan chain optimization and TAM optimization are NP-hard problems. Addressing wrapper scan chain optimization or TAM optimization separately leads to SOC test time sub-optimal. This paper presents a TWC&S (TAM/wrapper co-optimization and scheduling) algorithm for multi-clock SOC after combining the advantages of...
The paper presents a reverse SoC TAM design based dual-balanced strategy, which is on the basis of IEEE1500. Firstly test scheduling is executed according to the conceptual TAM architecture that is physically realizable, and then the real TAM architecture can be reversely established according to the test scheduling result. Since the test scheduling is not limited by TAM architecture, the test scheduling...
Test time optimization is necessary for modular testing of hierarchical system-on-chip (SOC) that contain embedded IP core. In this paper, we consider the case of non-interactive design transfer between IP core vendor and IC integrator. We proposes a method based on genetic algorithm which can efficiently optimize the test time of hierarchical SOC. Utilizing international reference circuit provided...
Power consumption during testing is becoming a primary concern. In this paper, an adjustable clock scan structure is presented. It can significantly reduce the peak power consumption during testing. The adjustable clock controlling multiple scan chains is used to reduce SA (switching activity) and avoid simultaneous shifting operation. Compared with exiting techniques of low power scan testing, the...
With the rapid development of IC design methods and manufacturing technologies, the scale of IC is becoming lager and lager, and the design method of system on chip (SoC) has been widely adopted. In the design process of SoC, the test problem is viewed as the bottleneck of the SoC development; and it is a challenge to test the IP (intellectual property) cores which are embedded deeply in the SoC especially...
Along with the development of the multi-core system, the testability of circuit faces many new challenges. Relay wave propagation test of arrays (RWPA) has many advantages in single-chain and multi-chain boundary scan (BS) circuit. In this paper, the improved single-chain RWPA is tentatively applied to the multi-core BS architecture, to reduce the test time and increase the fault coverage. As an experiment,...
With the increasing complexity and chip scale of SoC, the test problem is becoming more difficult and important. Adding DFT (design for testability) in SoC design period has become the main method for solving the test problem. Based on analyzing some common DFT structures such as Fscan-Bscan, Fscan-Tbus, and the standard for embedded core test (SECT) IEEE P1500, a system-level mixed DFT-TAM (test...
The demands for more powerful products and the huge capacity of today' s silicon technology move system-on-chip (SoC) designs from the leading-age to mainstream design practice. The one at the very top of the list of challenges to be solved for SoC design is verification. General agreement among many observers is that verification consumes at least 70 percent of whole design percent. SoC verification...
The mRNA differential display technique has several advantages over conventional subtractive hybridization due to its simplicity and high sensitivity. However, the relatively high incidence of false positive bands makes it more difficult to identify cDNAs derived from differential display, especially when subsequent large scale screening is required to isolate specific genes of interest. In...
We have isolated 52 mouse cardiac troponin-T-encoding cDNA clones (TnT) by specific antibody screening of a λZAPII expression library. Sequencing data from the large sample of independent cDNAs demonstrated relationships among the expression of four alternatively-spliced exons of the cardiac TnT gene, producing seven classes of cDNAs encoding four protein isoforms differing in two variable regions...
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