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High-energy cosmic radiation is the major source of soft errors in SRAMs that can cause multi-bit upset around the location of the strike. In this paper, we generalize the coding problem for error detection and correction of both local (burst) and global (random) errors. We suggest using error-locality-aware codes for SRAM memories to correct single-bit or multi-bit upsets as well as physical defects...
The yield and cost of a multi-core chip improve significantly through the addition of some spare cores in the system. In this paper, we model the manufacturing and service cost of an NoC with spare wires and routers as well as spare cores. We apply our analysis on an exemplary 9-core processor and on an Intel 80-core processor, and show that a spare scheme can significantly improve the reliability,...
It becomes increasingly difficult to achieve a high manufacturing yield for multi-core chips due to larger chip sizes, higher device densities, and greater failure rates. By adding a limited number of spare cores to replace defective cores either before shipment or in the field, the effective yield of the chip and its overall cost can be significantly improved. In this paper, we propose a yield and...
In IEEE 802.16 standard, the performance of the subscriber station (SS) MAC has to meet the timing constraints for the uplink and downlink transmissions. This requirement implies hardware acceleration of some protocol components through a precise hardware-software partitioning. In this paper, we first model the behavior of the system through high level specification and description language (SDL)...
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