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We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through the trade off relation between reducing...
A raised source/drain extension (RSDE) pFET on (110) Si wafer is demonstrated for the first time with in-situ doped selective epitaxy technology. Roll-off has been effectively improved, resulting from the elimination of ion channeling in (110) Si. Due to the hole mobility enhancement and parasitic resistance reduction, ion of 389muA/mum (Vd= -1.0 V) has been achieved at Lmin around 30nm extracted...
We propose HfSix/HfO2 gate stacks as the most suitable combination for high performance nMOSFETs. An equivalent work function (WF) to n+poly-Si was obtained by controlling Hf/Si ratio of the electrode. The highest electron mobility ever reported was achieved in the thinner Tinv region down to 1.6 nm by low temperature process without using plasma nitridation both for metal and high-k fabrication....
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