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Dynamically reconfigurable hardware allows for implementing systems that can be adapted at run-time according to the needs of the user. This paper presents an architecture that is composed of multiple FPGAs that are connected to an embedded processor. Thus, the architecture is referred to as a multi-FPGA clustered architecture (MFCA). All FPGAs can be partially and dynamically reconfigured to integrate...
Partial and dynamic reconfiguration significantly enhances the potential of FPGAs, which has been shown in various prototypic implementations in the past. In this paper the authors introduce a new methodology that eases the design of dynamically reconfigurable systems. It is based on a layer model that systematically abstracts from the underlying reconfigurable hardware to the application that wants...
Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip buses and...
Modern FPGAs, such as the Xilinx Virtex-II series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) during run-time. To enable communication with these modules and for controlling purposes, dedicated access to each module as well as dedicated signals to control the global communication are required. This paper discusses several...
Reconfigurable hardware, and particularly field programmable gates arrays (FPGAs) allow the acceleration of digital control algorithm for mechatronic systems by exploiting their intrinsic parallelism. FPGAs also allow an efficient use of resources and flexible designs by using partial and dynamic reconfiguration. However, fully utilization of those benefits is often prevented by the necessary expertise...
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