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We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from...
We report a record setting low NMOS contact Rc of 2e−9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e−9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity...
Low specific contact resistivity (7E-9 Ohm.cm2) was achieved for contacts with TiSix to in-situ epitaxially doped Si:P n-SD regions by use of Se implantation prior to Ti deposition. The key to this achievement is the optimization of implant energy and dose, and use of millisecond laser anneal to heal the implant damage, while allowing sufficient inter-mixing of Ti, Si, Se and P atoms across a smooth...
Contact resistivity (ρC) reduction for n-SD (source/drain) with Se+ implant was evaluated for different integration schemes. It is found that Se+ implant energy is one of the most critical process parameters for ρC improvement, achieved by placing the Se+ peak close to silicide (TiSi2 or NiPtSi)/Si interface and minimized implant damage. Recovery of implant damage to silicide and n-SD region was achieved...
The development of the MilliSecond Anneals (MSA) technology allows the use of short dwell time coupled with a high peak temperature in order to significantly reduce the global thermal budget. These points are fundamental in the phase transformation occurring in silicide materials: the high temperature allows the phase change and the short dwell time reduces the materials ability to diffuse and create...
As CMOS device dimensions shrink toward the 45nm technology node, the junction depth of the source/drain extensions must decrease to 7–12nm in order to minimize short channel effects. Simultaneously, the desire for high transistor drive currents and fast device performance leads to the requirement of a maximum PMOS extension sheet resistance of 830Ω/□. In order to meet the junction depth requirement,...
Laser annealing is one of the process solutions to enable ultra shallow junction (USJ) formation for the 45 nm technology node. However, variations in the front-side optical properties of device wafers cause large temperature variations on the wafer surface which, in turn, cause large variations in activation of the dopants that form the junction. As a result, pyrometry and closed loop temperature...
Since the requirements for the S/D extensions for future devices become more and more severe with respect to activation and vertical abruptness, a huge effort has been done to develop ultra-fast annealing techniques such as laser annealing. Due to the fact that only the surface layers are heated, the Si wafer serves as a heat sink. Hence, extremely fast cooling rates can be obtained resulting in a...
The continued scaling of devices in accordance with Moore's law requires activation of some implants such as the source-drain extensions, SDEs, with as little diffusion as possible. New options in thermal processing are described and compared. Thermal flux annealing is the regime where power density is high enough to cause local heating but not so high as to eliminate heat transfer entirely. If energy...
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