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Designing linear transmitters became mandatory to cater with high data rates applications and this trend is increasing, especially with 5G. This leads to a huge amount of energy consumption and important environmental challenges. For RF design point of view, the issue is improving energy efficiency, especially in user mobile equipment. This work proposes an original linear green RF transmitter system...
A fully integrated power amplifier using a power cell switching technique, implemented in 65 nm CMOS technology is presented. The main objective of the proposed architecture is to significantly improve the efficiency at high power back-off. To do so, distributed active transformers are used as the splitter, the combiner and the DC bias feed to partition the power requirements among the parallelised...
In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA Zero-Intermediate Frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator and a digital stage adjusting the phase rotation around...
A fully CMOS transmitter including a power amplifier (PA) using a Cartesian Feedback (CFB) technique is presented. This system aims at improving the linearity of the transmitter, designed in 65nm CMOS technology from STMicroelectronics, essentially the power amplifier linearity. This transmitter delivers a maximum output power of 23dBm. Thanks to this linearization technique, the ACPR has been improved...
This paper presents a 65nm CMOS-Power Amplifier (PA) designed for UMTS standard. It is based on a triple Stacked Folded pseudo-Differential Structure (triple SFDS) power stage and a differential cascode driver stage. The PA provides 31.5 dBm maximal output power (Pmax) with 20% of maximal power added efficiency (PAEmax) at 1.95 GHz. The linear gain is 37 dB and the compression point (OCP1) is 29.5...
This paper presents the current status of multi-standard transmitters and receivers in terms of integration level and its impact on the cost associated with handset terminals dedicated to both voice and digital data transmissions. The actual RF system architecture trends such as multi-radios, reconfigurable radios and software oriented radios, namely software defined radio and full software radio,...
Nowadays, mobile handsets have to deal with several challenges. First of all, a good efficiency is essential in order to save power and battery life-time. Then, to cater to multi-standards operation which provide very high data rates, strong linearity performances are mandatory, to the expense of transmit front-end efficiency. As RF Power Amplifiers (PAs) are the most power consuming components, this...
We present the design of an ultra low power sixth-order Butterworth low pass GmC filter in 0.13 ??m CMOS process. A method to optimize the power consumption of a fully differential telescopic OTA is also presented to achieve an input linearity of 220 mVpp and transconductance value of 6 ??S. The OTA is then used to implement an ultra low power filter and to show the impact of parasitic capacitances...
This paper describes the techniques to design a SiGe power amplifier (PA) for millimeter wave (mmW) applications. The design methodology of a balanced four-stage common emitter circuit topology was reported. The power amplifier was fully integrated including matching elements and bias circuit. The matching networks use coplanar waveguide (CPW) lines and MIM capacitors. Design considerations including...
This paper presents a training in characterization of integrated circuits for millimeter-wave and power applications. The goal of this training is to initiate the student to millimeter-wave measurements. The training is based on high performance equipments like a VNA (Vector Network Analyzer) up to 110 GHz, two probe stations and a millimeter wave load-pull facility. The devices under test (DUT) are...
A study based on improving linearity of an integrated RF power amplifier (PA) has been done for W-CDMA standard. This power amplifier had been designed in 65 nm CMOS of STMicroelectronics under Cadence. The chosen linearization technique is a Cartesian Feedback (CFB). Thanks to this linearization technique, the ACPR has been improved by 22 dB at 5 MHz from the carrier for an output power of 18 dBm.
This paper presents a 65 nm CMOS power amplifier (PA) using a coupled transformer. The PA is based on an original structure, called stacked folded fully differential structure (SFFDS). It is applied to the UMTS W-CDMA standard. The parallel SFFDS power amplifier provides 30.5 dBm of output power with 20% of power added efficiency (PAE) at 1.95 GHz. The output compression point (OCP1) is 27.5 dBm and...
We present a method to automatically match a system to the load variation accurately with a very short matching time for ultra low power medical applications. A demonstrator was fabricated and an experimental set-up in the medical implant communication system (MICS) frequency band of 402-405 MHz was realized including a pacemaker antenna prototype immersed on a homogeneous lossy liquid. The matching...
The following discussion presents a novel technique of power management in TX 4G transmit path, capable of efficiently handling wide channel bandwidth and high peak-to-average-power-ratio (PAPR). It consists in a power adaptive closed loop, based on a switched multi-cell power amplifier (PA) core and a novel delta-sigma control loop topology. This work was carried out with a ST microelectronics SiGe...
This paper presents a 65 nm CMOS-power amplifier (PA) designed for mobile communications.The PA is based on a new structure, the stacked folded fully differential (SFFD) which is inspired by a push-pull structure. The PA is designed for the UMTS W-CDMA standard which requires linearity from -20 dBm to 24 dBm output power. The power amplifier provides 31 dBm output power with 26% of power added efficiency...
A 65 nm CMOS, 60 GHz fully integrated power amplifier (PA) from STMicroelectronics has been designed for low cost Wireless Personal Area Network (WPAN). It has been optimized to deliver the maximum linear output power (OCP1) without using parallel amplification topology. The simulated OCP1 is equal to 8.9 dBm with a gain of 8 dB. To obtain good performances and consume an ultra compact area of silicon,...
A 24 GHz, +18.0 dBm fully-integrated power amplifier (PA) with 50 Omega input and output matching is designed in 0.13 mum SiGe BiCMOS process. The power amplifier features a peak power gain of 7.8 dB with 15.89 dBm output power at 1 dB compression and a maximum single-ended output power of +18.0 dBm with 25.9% of power-added efficiency (PAE). The power amplifier uses a single 1.8 V supply and was...
This paper investigates the feasibility of designing a RF TX architecture based on a Power VCO, operating at 1.95 GHz for UMTS/WCDMA standard. The Power VCO uses 2.5 V supply voltage and is designed using 65 nm CMOS technology from ST Microelectronics. The Power VCO is made up of an oscillating Power Amplifier (PA). In order to fulfil UMTS/W-CDMA requirements, especially on output power with regards...
To exploit the unlicensed band at frequencies around 60 GHz, a certain number of design rules is considered. This paper highlights the difficulties to design a millimeter CMOS power amplifier (PA). A model of a compact inductor and interconnect lines is detailed. This model takes into account substrate and resistive parasitic. A 65 nm CMOS technology from STMicroelectronics has been used. Innovative...
This paper describes the feasibility of a power amplifier (PA) in 0.13mum CMOS technology from STMicroelectronics. It is designed for the UMTS W-CDMA standard. This power amplifier provides 33 dBm maximal output power with 60% of power added efficiency (PAE) at 1.95 GHz. This standard requires linearity from -20 dBm till 24 dBm output power. The linear gain is 16.7 dB and the compression point (OCP1)...
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