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High performance Ge CMOS with quantum well-structured channels has been successfully realized using a single MoS2 capping layer. Thanks to a large valence band offset (0.43 eV) and conduction band offset (0.5 eV) between the two-layers-thick MoS2 and the Ge substrate, both holes and electrons within the Ge p- and n-MOSFETs are confined into Ge channels and the scattering due to the traps in gate stacks...
In this paper, we present first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by direct wafer bonding (DWB) process using InGaAs channels grown on 4-inch Si donor substrates with III–V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated...
MOSFETs and Tunnel-FETs (TFETs) based on arrays of nanowires (NWs) with 10 × 10 nm2 cross-section have been fabricated with strained silicon on insulator substrates. MOSFET devices show near ideal subthreshold slope close to 60 mV/dec proving excellent channel control achieved by high-klmetal gate stack. As expected fundamental differences between MOSFETs and TFETs in current-voltage characteristics...
For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and drive current over our best poly-gate 45 nm-node nMOSFET with SMT and tensile liner stressors. In addition, eSi:C showed better scalability than SMT plus tensile liner stressors from 380 nm to 190 nm poly-pitches.
We report a successful implementation of epitaxially grown Phosphorus-doped (P-doped) embedded SiC stressors into SOI nMOSFETs. We identify a process integration scheme that best preserves the SiC strain and minimizes parasitic resistance. At a substitutional C concentration (Csub) of ~1.0%, high performance nFETs with SiC stressors demonstrate ~9% enhanced Ieff and ~15% improved Idlin against the...
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