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A 50 V, 0.56 m Omega cm/sup 2/ vertical power DMOSFET fabricated using selectively silicided gate and source contact regions is reported. The gate-source isolation was provided by anisotropically etched oxide sidewall spacers. This new device structure lowers the source contact resistance considerably by providing a larger contact area and improves the distributed gate RC propagation delay by lowering...
A novel high-frequency power FET technology is reported that is based on the application of blanket-deposited LPCVD (low-pressure chemical vapor deposition) WSi/sub 2/ to reduce the gate sheet resistance and selectively deposited LPCVD W to improve the source and gate contact resistances. Power FETs capable of blocking 45 V and 90 V in the off-state have been fabricated using this technology, with...
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