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In this paper, we investigate Bias Temperature Instabilities (BTI) in Ωfet nanowires exhibiting a very low interface states density ∼1010cm2. Positive BTI is independent of the transistor width W and meets the 10year lifetime requirements. On the other hand, Negative BTI is enhanced in narrow devices. To explain this effect, several scenarios are discussed by means of dedicated measurements i.e. charge...
In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17 ??/Vdd 1.1 V and 29 ??/Vdd 1.8 V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators...
In this work, 3D monolithic cells have been demonstrated, featuring the first perfectly crystalline upper active layer thanks to wafer bonding. The low temperature process (<600degC) of the top GeOI and SOI MOSFETs leads to well behaved characteristics and allows preservation of bottom FETs performance. The benefit of the decreased process temperature is highlighted by improved short channel effect...
In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0...
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