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Reduction in the latency (end-to-end latency and network latency), loss probability, energy consumption and response time are the basic parameters, which are considered by the researchers for the optimization of the networks-on-chip topologies. Different cores communicate at different rates with each other. Some cores communicate at a very rapid rate whereas some rarely communicate to each other....
Mapping of the tasks onto the core is the main aim of the paper. So there is need to design such an algorithm that the tasks should not wait in the queue for long time. Our main focus is to design an algorithm that should concentrate on the load balancing, such that the problem of overheating of the cores is reduced. For this purpose different researchers have given different mapping algorithms. It...
The Control system algorithms implementation in Networks-on-Chip (NoC) is the best way to address the various issues like power consumption, congestion control, and data packet loss. In this paper, we present the modern control system mapped on NoC. The concept of on chip implementation of Networked Control Systems (NCS) started to grow because of its potential in various applications, it also provided...
Packet-switched networks-on-chips (NoCs) are efficient communication architectures for future multiprocessors system-on-chip (MP-SoC) platforms. However the run-time management of their communication, especially flow control from individual intellectual property (IP) in an NoC which contains large number of IPs, is a challenging task. This paper proposes a state space model for NoC with state observer...
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